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| 5V/3.3V /2, /4, /8 CLOCK GENERATION CHIP ClockWorksTM SY10EL34/L SY100EL34/L FEATURES s s s s s 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors DESCRIPTION The SY10/100EL34/L are low skew /2, /4, /8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/ sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system. s Available in 16-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM Q0 Q0 1 Q /2 R QD 16 15 14 13 Q /4 R VCC EN NC CLK CLK VBB MR VEE 2 VCC 3 R Q1 Q1 4 5 12 11 10 VCC 6 Q2 Q2 7 Q /8 R 8 9 SOIC TOP VIEW PIN NAMES Pin CLK EN MR VBB Q0 Q1 Q2 Function Differential Clock Inputs Synchronous Enable Master Reset Reference Output Differential /2 Outputs Differential /4 Outputs Differential /8 Outputs Rev.: F Amendment: /0 1 Issue Date: August, 1998 Micrel ClockWorksTM SY10EL34/L SY100EL34/L TRUTH TABLE CLK Z ZZ X EN L H X MR L L H Function Divide Hold Q0-2 Reset Q0-2 NOTE: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition DC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = -40C Symbol IEE VBB IIH Parameter Power Supply Current 10EL 100EL Min. -- -- Typ. -- -- -- -- -- Max. 49 49 Min. -- -- TA = 0C Typ. -- -- -- -- -- Max. 49 49 TA = +25C Min. -- -- Typ. -- -- -- -- -- Max. 49 49 TA = +85C Min. -- -- Typ. -- -- -- -- -- Max. 49 54 -1.19 -1.26 150 Unit mA V A Output Reference 10EL -1.43 Voltage 100EL -1.38 Input High Current -- -1.30 -1.38 -1.26 -1.38 150 -- -1.27 -1.35 -1.26 -1.38 150 -- -1.25 -1.31 -1.26 -1.38 150 -- NOTE: 1. Parametric values specified at: 5 volt Power Supply Range 3 volt Power Supply Range 100EL34 Series: 10EL34 Series 10/100EL34L Series: -4.2V to -5.5V. -4.75V to -5.5V. -3.0V to -3.8V. AC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = -40C Symbol tPLH tPHL tskew tS tH VPP VCMR tr tf Parameter Propagation Delay to Output CLK MR Within-Device Skew(2) Set-up Time EN Hold Time EN Minimum Input Common Mode Swing(3) Range(4) Min. 960 650 -- 400 200 250 -1.3 275 Typ. 1100 800 -- -- -- -- -- 400 Max. 1200 1010 50 -- -- -- -0.4 525 Min. 960 650 -- 400 200 250 -1.4 275 TA = 0C Typ. 1100 800 -- -- -- -- -- 400 Max. 1200 1010 50 -- -- -- -0.4 525 TA = +25C Min. 960 650 -- 400 200 250 -1.4 275 Typ. 1100 800 -- -- -- -- -- 400 Max. 1200 1010 50 -- -- -- -0.4 525 TA = +85C Min. 960 650 -- 400 200 250 -1.4 275 Typ. Max. 1100 1200 800 1010 -- -- -- -- -- 400 50 -- -- -- -0.4 525 ps ps ps mV V ps Unit ps Output Rise/Fall Times Q (20% - 80%) NOTES: 1. Parametric values specified at: 5 volt Power Supply Range 3 volt Power Supply Range 2. Skew is measured between outputs under identical transitions. 3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = -3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V - IVCMR (min)I. 100EL34 Series: 10EL34 Series 10/100EL34L Series: -4.2V to -5.5V. -4.75V to -5.5V. -3.0V to -3.8V. 2 Micrel ClockWorksTM SY10EL34/L SY100EL34/L TIMING DIAGRAM Internal Clock Disabled Internal Clock Enabled CLK Q0 Q1 Q2 EN The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. PRODUCT ORDERING CODE 3.3V Ordering Code SY10EL34LZC SY10EL34LZCTR SY100EL34LZC SY100EL34LZCTR Package Type Z16-2 Z16-2 Z16-2 Z16-2 Operating Range Commercial Commercial Commercial Commercial VEE Range (V) -3.0 to -3.8 -3.0 to -3.8 -3.0 to -3.8 -3.0 to -3.8 5V Ordering Code SY10EL34ZC SY10EL34ZCTR SY100EL34ZC SY100EL34ZCTR Package Type Z16-2 Z16-2 Z16-2 Z16-2 Operating Range Commercial Commercial Commercial Commercial VEE Range (V) -4.75 to -5.5 -4.75 to -5.5 -4.2 to -5.5 -4.2 to -5.5 3 Micrel ClockWorksTM SY10EL34/L SY100EL34/L 16 LEAD SOIC .150" WIDE (Z16-2) Rev. 02 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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